Lexra Announces RISC-DSP Core Based on MIPS Instruction Set Architecture

	Lexra Announces RISC-DSP Core Based on MIPS Instruction Set Architecture

	Company:	Lexra
	Category:	Microcontroller Cores (new Products)
	Date:	05-May-1999

	Waltham, MA - (Microcontroller.com) - -Lexra, a Massachusetts-based firm that licenses processor cores for embedded applications based on the popular MIPS architecture, has announced the LX5280, the industry's first RISC-DSP core based on the MIPS® instruction set architecture. The LX5280 supports Lexra's RADIAX™ DSP instruction extensions. It promises to deliver comparable performance to TI's C6201, at less than 20% of the die area and power dissipation. The LX5280 RISC and DSP instructions are tightly integrated (in the same stream), that is, they share the same ALU and register files. Benchmark performance has it rated at about 90 BDTi mark, just 10% less than TI's C6201. The LX5280's integration of RISC and DSP features allows the processor to perform control-oriented tasks while simultaneously managing the real-time processing of analog data. The LX5280 uses a dual-issue, seven-stage pipeline, and supports Lexra's RADIAX DSP extensions to the MIPS instruction set. Based on Lexra's high performance 32-bit R3000®-class CPU, the LX5280 adds dual 16-bit/32-bit multiply-accumulate (MAC) units to the MIPS core. The MAC units are pipelined to provide optimized single-cycle 16-bit multiply-accumulate operations. The LX5280 supports MIPS EJTAG in-circuit emulation interface, and also supports MIPS16® code compression. In 0.18-micron technology, the LX5280 achieves a system clock speed of 200MHz, with a peak computational power of 400 million multiply-accumulate (MAC) operations per second, comparable to the highest-performance DSPs available. The die size for the entire LX5280 processor subsystem will be approximately 6 mm², with an estimated power consumption of 225mW. The LX5280 is part of a new breed of processors, Microcontroller Signal Processors (MSP), putting it in the same segment as Infineon's TriCore and Hitachi's SH-DSP. Each Lexra core is available as a synthesizable RTL module or as a SmoothCore™, an optimized hard macro that has been ported to a specific silicon process. For ASIC prototyping and software development, Lexra's products are available on Programmable Logic Devices. The LX5280 RTL core will be available in November of 1999. License fees start at $495,000 plus unit royalty of $1.95 per chip. The RTL core includes the Verilog database, synthesis scripts and a regression suite. The SmoothCore™ version of the LX5280 will be available in February 2000, and will include physical databases for major foundries. Development tool and software support for Lexra cores come from 3rd party MIPS tool suppliers such as Green Hills Software, California Advanced Software Tools, and Embedded Performance Inc. Note: Lexra provides synthesizable cores for its partners and does not manufacture packaged silicon. Contact Lexra for further product and licensing information,
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Lexra Announces RISC-DSP Core Based on MIPS Instruction Set Architecture

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