Embedded IP

MIPS Introduces New 550MHz Embedded Microarchitecture

SAN JOSE, June 16, 2003 - MIPS Technologies, Inc. (Nasdaq: MIPS, MIPSB), today introduced a new high-performance microarchitecture that will address the changing economics of SOC design and help engineers increase profitability by extending their product’s lifecycle.  The MIPS32™ 24K™ microarchitecture is the foundation for MIPS Technologies’ next-generation of  high-performance, synthesizable cores, and extends the company’s leadership as the provider of industry-standard performance technology to semiconductor and system companies.

The 625MHz MIPS32K-24K

“The high performance and programmable capabilities offered by the 24K microarchitecture enable system designers to add the features that their customers demand in software instead of using expensive mask sets,” said Mike Uhler, CTO for MIPS Technologies.  “Combined with the more than 20 years of software development around the industry-standard MIPS architecture, customers can leverage the investment in operating systems, optimized protocol stacks and tool chains to reduce overall product development costs while getting to market faster.”

Applications
The MIPS32 24K microarchitecture is targeting digital consumer devices such as set-top boxes and digital televisions, where high levels of system performance and application configurability are required.  Furthermore, the 24K microarchitecture is also targeting networking infrastructure protocols that require software programmability.

This new microarchitecture is based upon customer feedback requirements for digital consumer and networking products. It is designed to scale below 0.13 micron technologies and features architectural enhancements and configurable features from MIPS Technologies while maintaining compatibility with the standard MIPS32 architecture.

Features of the MIPS32 24K Microarchitecture
The new MIPS32 24K microarchitecture is ideal for products requiring high frequency operation on a low power budget. As with all MIPS-based™ technologies, it offers broad tool and software support only available to products based upon an industry-standard architecture.  It delivers the highest performance in its class with unique features such as:

Scalable performance:

• Single issue, 8-stage pipeline
• Operating performance ranges from 400 to 550 MHz (worst case) in a 0.13u processes
• Hardware-based cache coherency to support multi-processor scaling
• Configurable memory management unit with TLB or fixed mapping
• 64-bit high performance memory subsystem with up to six outstanding read transactions

• Release 2 implementation with features such as multiple general purpose register sets and support for vectored interrupts
• Reduced interrupt latency
• Code compression technology with MIPS16e™ ASE
• Fits industry-standard SOC construction methodologies:
• Fully synthesizable
• OCP high-speed point-to-point on-chip interconnectOptimized for market-specific implementations:
• User extendable instructions with the CorExtend™ feature
• Floating point support that is fully compliant with IEEE 754
• Advanced power management features

• Application configurability to optimize area and features
• Compact core  optimal die size
• Code size efficiency

• Maintains compatibility with the industry-standard MIPS32 architecture
• Enables access to the broad array of third party tools and software
• Leverages the extensive software investments in the MIPS32 architecture, such as middleware and application software, made by MIPS® partners during the past twenty years